;****************************************************************************** ;****************************************************************************** ;* D E F I N I T I O N S * ;****************************************************************************** ;****************************************************************************** ; copyright PMB 2006 ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM 1FFH ; __BADRAM 08H-09H, 13H-14H, 1BH-1DH ; __BADRAM 88H-89H,8FH-91H, 93H-97H, 9AH-9DH, C0H-EFH ; __BADRAM 105H, 107H-109H, 110H-11FH ; __BADRAM 185H, 187H-189H, 18EH-19FH, 1C0H-1EFH ;========================================================================== ; Configuration Bits ;========================================================================== ORG 2007H ; configuration data CONFIG DWM 3F72H ; without code protect ;CONFIG DWM 0D45H ; with code protect _CP_ALL EQU 0FCFH ; _CP_OFF EQU 3FFFH ; _DEBUG_ON EQU 37FFH ; _DEBUG_OFF EQU 3FFFH ; _WRT_ENABLE_ON EQU 3FFFH ; _WRT_ENABLE_OFF EQU 3DFFH ; _CPD_ON EQU 3EFFH ; _CPD_OFF EQU 3FFFH ; _LVP_ON EQU 3FFFH ; _LVP_OFF EQU 3F7FH ; _BODEN_ON EQU 3FFFH ; _BODEN_OFF EQU 3FBFH ; _PWRTE_OFF EQU 3FFFH ; _PWRTE_ON EQU 3FF7H ; _WDT_ON EQU 3FFFH ; _WDT_OFF EQU 3FFBH ; _LP_OSC EQU 3FFCH ; _XT_OSC EQU 3FFDH ; _HS_OSC EQU 3FFEH ; _RC_OSC EQU 3FFFH ; ;****************************************************************************** ; RAM VARIABLE ASSIGNMENTS ;---------------------------------------- ;---------------------------------------- ; Bank 0 = GP registers (STATUS:7 clear for FSR use) ; 0000H to 006FH = RAM ; 0070h to 007Fh = shared with other banks ORG 0020H ; user RAM start of bank-0 SAV_ST1 DFS 1 ; 20 ; place to save STATUS during interrupts SAV_FSR DFS 1 ; 21 ; place to save FSR during interrupts SAV_PC1 DFS 1 ; 22 ; place to save PCLATH during interrupts TIC DFS 1 ; 23 ; Number of 10ms intervals/sec 0-99. SEC DFS 1 ; 24 ; clock seconds MIN DFS 1 ; 25 ; clock minutes HRS DFS 1 ; 26 ; clock hours FLAGS1 DFS 1 ; 27 ; gp flags register #1 FLAGS2 DFS 1 ; 28 ; gp flags register #2 FLAGS3 DFS 1 ; 29 ; gp flags register #3 FLAGS4 DFS 1 ; 2A ; gp flags register #4 FLAGS5 DFS 1 ; 2B ; gp flags register #5 ISRCNT DFS 1 ; 2C ; ISR cycle counter GPTIM1 DFS 1 ; 2D ; general purpose timer (dallas routines) GPTIM2 DFS 1 ; 2E ; general purpose timer (eeprom) BITCNT DFS 1 ; 2F ; I2C bit counter RDBCNT DFS 1 ; 30 ; read byte counter (eeprom access) ATTCNT DFS 1 ; 31 ; attempt counter (eeprom access) ; ***** these must only be used within interrupts ***** TMP1 DFS 1 ; 32 ; subroutine variable (application) TMP2 DFS 1 ; 33 ; subroutine variable () TMP3 DFS 1 ; 34 ; subroutine variable (SER_RX) TMP4 DFS 1 ; 35 ; subroutine variable (ADC) ; ***** these must not be used within interrupts ***** VAR1_L DFS 1 ; 36 ; variable 1 low (DSIDS, DSRESET, DSTXD, DSRXD, DAT_TX) VAR1_H DFS 1 ; 37 ; variable 1 high (DSTXD, DSRXD, DAT_TX) VAR2_L DFS 1 ; 38 ; variable 2 low (SIN_TX) VAR2_H DFS 1 ; 39 ; variable 2 high (SIN_TX) VAR3_L DFS 1 ; 3A ; variable 3 low (SIN_TX) VAR3_H DFS 1 ; 3B ; variable 3 high VAR4_L DFS 1 ; 3C ; variable 4 low VAR4_M DFS 1 ; 3D ; variable 4 medium VAR4_H DFS 1 ; 3E ; variable 4 high (AS_B_2, AS_B_3, TX_HEX) EPC1 DFS 1 ; 3F ; eeprom write delay, triac drive delay EPC2 DFS 1 ; 40 ; eeprom write delay TUNE1 DFS 1 ; 41 ; triac driver tuning value PAUL1 DFS 8 ; 42 ; debug register PAUL2 DFS 1 ; 4A ; debug register PAUL3 DFS 1 ; 4B ; debug register ADCRES1 DFS 1 ; 4C ; ADC-0 result (input D2) potentiometer ADCRES2 DFS 1 ; 4D ; ADC-1 result (input D8) ADCRES3 DFS 1 ; 4E ; ADC-2 result (input D3) ADCRES4 DFS 1 ; 4F ; ADC-3 result (input D9) ADCRES5 DFS 1 ; 50 ; ADC-4 result (internal temperature) ;************ ; heat pump controller specific TVAR_1 DFS 1 ; 51 ; target temperature TVAR_2 DFS 1 ; 52 ; actual temperature TVAR_3 DFS 1 ; 53 ; input value (pot) TVAR_4 DFS 1 ; 54 ; variable TVAR_5 DFS 1 ; 55 ; variable TVAR_6 DFS 1 ; 56 ; variable TVAR_7 DFS 1 ; 57 ; variable TVAR_8 DFS 1 ; 58 ; variable TVCHK1 DFS 1 ; 59 ; display variable checksum (for updates) OPCNT1 DFS 1 ; 5A ; output counter STATS2 DFS 1 ; 5B ; status flags CLCNT1 DFS 1 ; 5C ; core cycle counter ;************ ORG 006FH ; within bank-0 SAV_W1 DFS 1 ; 6F ; place to save W during interrupts ;************ ; Common to all banks ; This batch of locations appears at the top of all memory banks ORG 0070H ; RAM shared across banks ; TXMSG & RXMSG are used to transfer data (messages) etc. between banks. ; This includes data sent to the triac module and data loaded from and saved to eeprom. ICD2_R1 DFS 1 ; 70 ; reserved by ICD2, debugger TXMSG DFS 4 ; 71 ; TX msg buffer + I2C registers RXMSG DFS 4 ; 75 ; RX message buffer ; EXPCMD DFS 1 ; 79 ; last command received ; 7Fh is end of Bank-0 RAM ;************ ; these addresses are shared with the 4-byte "TX msg buffer" ORG 0070H ; (RAM shared accross banks) ICD2_R1 DFS 1 ; ; reserved by ICD2, debugger I2CADD DFS 1 ; TXMSG1+0 ; address in I2C device I2CWRK DFS 1 ; TXMSG1+1 ; I2C working register TXDAT DFS 1 ; TXMSG1+2 ; I2C tx data byte RXDAT DFS 1 ; TXMSG1+3 ; I2C rx data byte ;---------------------------------------- ;---------------------------------------- ; Bank 1 = RS-232 comms buffers (STATUS:7 clear for FSR use) ; 0A0H to 0EFH = RAM ; 0F0h to 0FFh = shared with other banks ; Bank-1 is used RS-232 communications buffers. The TX buffer is large so that ; reasonably large screen control and text blocks can be output without too ; much waiting between buffer reloads. The RX buffer is larger enough to hold ; a couple of incomming commands. ORG 0A0H ; user RAM start of bank-1 TX_BUF DFS 50D ; A0 ; serial TX buffer (48 data bytes) TX_BND DFS 1 ; D2 ; last byte of buffer RX_BUF DFS 15D ; D3 ; serial RX buffer (16 data bytes) RX_BND DFS 1 ; E2 ; last byte of buffer TX_WPTR DFS 1 ; E3 ; byte offset pointer TX_RPTR DFS 1 ; E4 ; byte offset pointer RX_WPTR DFS 1 ; E5 ; byte offset pointer RX_RPTR DFS 1 ; E6 ; byte offset pointer RX_TIM DFS 1 ; E7 ; reception timer ; variables (not to be used within interrupts) TBLSEL DFS 1 ; E8 ; table select FLAGS6 DFS 1 ; E9 ; gp flags register #6 (serial comms) B1TMP1 DFS 1 ; EA ; temporary variable ORG 0EFH ; within bank-1 SAV_W1B DFS 1 ; EF ; duplicate to save W during "EXT" INT ;---------------------------------------- ;---------------------------------------- ; Bank 2 = EEPROM buffer (STATUS:7 set for FSR use) ; 110H to 16FH = RAM ; 170h to 17Fh = shared with other banks ; Bank-2 is used with PIC internal eeprom to save and restore configurations and ; with external eeprom to read and write data up to 8-bytes at a time. ; This can save logging data to external eeprom or read a token based command ; language. ORG 110H-100H ; user RAM start of bank-1 ; configuration & presets stored in EEPROM EESAV_S ; save to eeprom (block begin) DSROM1 DFS 8D ; 110 ; dallas rom code #1 DSROM2 DFS 8D ; 118 ; dallas rom code #2 FLAGS8 DFS 1 ; 120 ; configuration flags #8 FLAGS9 DFS 1 ; 121 ; configuration flags #9 UIDC DFS 2 ; 122 ; unit id (2 bytes) SVAR_1 DFS 1 ; 124 ; variable SVAR_2 DFS 1 ; 125 ; variable SVAR_3 DFS 1 ; 126 ; variable SVAR_4 DFS 1 ; 127 ; variable SVAR_5 DFS 1 ; 128 ; variable SVAR_6 DFS 1 ; 129 ; variable SVAR_7 DFS 1 ; 12A ; variable SVAR_8 DFS 1 ; 12B ; variable SVAR_9 DFS 1 ; 12C ; variable SVAR_10 DFS 1 ; 12D ; variable SVAR_11 DFS 2 ; 12E ; time variable (00:00 to 23:59) SVAR_13 DFS 2 ; 130 ; time variable (00:00 to 23:59) SVAR_15 DFS 2 ; 132 ; time variable (00:00 to 23:59) SVAR_17 DFS 2 ; 134 ; time variable (00:00 to 23:59) SVAR_19 DFS 2 ; 136 ; time variable (00:00 to 23:59) SVAR_1B DFS 2 ; 138 ; time variable (00:00 to 23:59) EESAV_E ; eeprom read/write buffer (8-bytes) EE_RWB DFS 8 ; 13A ; control flags EERW_RA DFS 1 ; 142 ; read address EERW_WA DFS 1 ; 143 ; write address EEAD_L DFS 1 ; 144 ; eeprom address low EEAD_H DFS 1 ; 145 ; eeprom address high ORG 160H-100H ; within RAM Bank-2 B2TMP1 DFS 1 ; 160 ; temp variable B2TMP2 DFS 1 ; 161 ; temp variable (internal eeprom access) B2TMP3 DFS 1 ; 162 ; temp variable (internal eeprom access) B2TMP4 DFS 1 ; 163 ; temp variable (internal eeprom access) B2TMP5 DFS 1 ; 164 ; temp variable (internal eeprom access) B2TMP6 DFS 1 ; 165 ; temp variable (internal eeprom access) WTEMP1 DFS 1 ; 166 ; temperature WTEMP2 DFS 1 ; 167 ; temperature STATS1 DFS 1 ; 168 ; controler status flags ORG 16FH-100H ; within RAM Bank-2 SAV_W1C DFS 1 ; 16F ; duplicate to save W during "EXT" INT ; NOTE: 16Fh = last usable RAM byte in bank-2 ;---------------------------------------- ;---------------------------------------- ; Bank 3 = not yet used (STATUS:7 set for FSR use) ; 190H to 1EFH = RAM ; 1F0h to 1FFh = shared with other banks ORG 190H-100H ; user RAM start of bank-1 ; put variables here ORG 1E5H-100H ; within bank-3 ICD2_R2 DFS 11 ; 1E5 ; reserved by ICD2, debugger ORG 1EFH-100H ; variables within bank-1 SAV_W1D DFS 1 ; 1EF ; duplicate to save W during "EXT" INT ;** conflicts with ICD2 debugger if interrupt occurs while accessing bank-3 ** ; NOTE: 1EFh = last usable RAM byte in bank-3 ;****************************************************************************** ;****************************************************************************** ; CONSTANTS ;****************************************************************************** ;****************************************************************************** D2 EQU 0H ; PORT-A analog (white/brown) pin-2 D8 EQU 1H ; PORT-A analog D3 EQU 2H ; PORT-A analog D4 EQU 3H ; PORT-A analog TMP_IP EQU 4H ; PORT-A analog temperature sensor SPARE_5V EQU 5H ; PORT-A input not used UI_CLK EQU 0H ; PORT B input expansion clock (interrupt) UI_DAT EQU 1H ; PORT B input expansion data DS_IP EQU 2H ; PORT-B input dallas RX DS_OP EQU 3H ; PORT-B output dallas TX NC_B4 EQU 4H ; PORT-B input n.c. LED_GN EQU 5H ; PORT-B output led NC_B6 EQU 6H ; PORT-B input n.c. LED_RD EQU 7H ; PORT-B output led EXT_IO EQU 7H ; PORT B output test point SI_CLK EQU 0H ; PORT C output 676-link clock (interrupt) SI_DAT EQU 1H ; PORT C output 676-link data SI_EN EQU 2H ; PORT-C output 676 outputs 2&3 enable CLK_I2C EQU 3H ; PORT-C output I2C DAT_I2C EQU 4H ; PORT-C input I2C EN_I2C EQU 5H ; PORT-C output I2C 0= write enable TXD EQU 6H ; PORT-C output RS-232 transmit data RXD EQU 7H ; PORT-C input RS-232 receive data DDRA_0 EQU 00011111B ; PORT-A data direction default DDRB_0 EQU 01010111B ; PORT-B data direction default DDRC_0 EQU 10010000B ; PORT-C data direction default